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. U 4 QL3012 pASIC 3 FPGA Data Sheet t e e h S ••••• • 12,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance a t a and High Density Eight Low-Skew Distributed Device .D Highlights w Networks w Two array clock/control networks available Performance & High Density wHigh to the logic cell flip-flop clock, set and reset 12,000 Usable PLD Gates with 118 I/Os
• • • 300 MHz 16-bit Counters,
m o c
400 MHz Datapaths • 0.