QL3040 - PLD Gate pASIC 3 FPGA Combining High Performance and High Density

QuickLogic Corporation

Features

0800 1.0600 1.0400 Kv 1.0200 1.0000 0.9800 www. DataSheet4U. com 0.9600 0.9400 0.9200 3 3.1 3.2 3.3 3.4 3.5 3.6 Supply Voltage (V) Figure 3: Voltage Factor vs. Supply Voltage Temperature Factor vs. Operating Temperature 1.15 1.10 1.05 1.00 0.95 0.90 0.85 -60 -40 -20 0 20 40 60 80 Kt Junction Temperature C Figure 4: Temperature Factor vs. Operating.

QL3040 pld gate pasic 3 fpga combining high performance and high density by QuickLogic Corporation - Datasheet Preview

Datasheet Details

Part number	QL3040
Manufacturer	QuickLogic Corporation
File Size	481.36 KB
Description	PLD Gate pASIC 3 FPGA Combining High Performance and High Density
Datasheet	QL3040 Datasheet

📁 Similar Datasheet

Part Number	Description	Manufacturer
QL3012	qASIC 3 FPGA	QuickLogic

Other Datasheets by QuickLogic Corporation

Part Number	Description
QL3004	PLD Gate pASIC 3 FPGA Combining High Performance and High Density
QL3004E	PLD Gate pASIC 3 FPGA Combining High Performance and High Density
QL3006	PLD Gate pASIC 3 FPGA Combining High Performance and High Density
QL3025	PLD Gate pASIC 3 FPGA Combining High Performance and High Density
QL3060	PLD Gate pASIC 3 FPGA Combining High Performance and High Density

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text

QL3040 pASIC 3 FPGA Data Sheet •••••• 40,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • 40,000 Usable PLD Gates with 252 I/Os • 300 MHz 16-bit www.DataSheet4U.com Eight Low-Skew Distributed Networks • Two array clock/control networks available Counters, 400 MHz Datapaths • 0.

Published: May 22, 2010 |