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PLL650-09 - Low Cost Network LAN Clock

Description

The PLL 650-09 is a low cost, low jitter, and high performance clock synthesizer.

With PhaseLink’s proprietary analog Phase Locked Loop techniques, the chip accepts 25.0 MHz crystal, and produces multiple output clocks for networking chips.

Features

  • w w Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. Advanced, low power, sub-micron CMOS processes. 25MHz fundamental crystal or clock input. 4 outputs fixed at 50MHz . Zero PPM synthesis error in all clocks. Ideal for Network switches. 3.3V operation. Available in 16-Pin 150mil SOIC. w . D at h S a t e e 4U . m o c PLL650-09 Low Cost Network LAN Clock PIN CONFIG.

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Datasheet Details

Part number PLL650-09
Manufacturer PhaseLink
File Size 359.02 KB
Description Low Cost Network LAN Clock
Datasheet download datasheet PLL650-09 Datasheet

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Other Datasheets by PhaseLink

Part Number Description
PLL650-02 Low EMI Network LAN Clock
PLL650-03 Low EMI Network LAN Clock
PLL650-04 Low EMI Clock
PLL650-05 Low EMI Network LAN Clock
PLL650-06 Network LAN Clock

Full PDF Text Transcription

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FEATURES • • • • • • • • w w Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. Advanced, low power, sub-micron CMOS processes. 25MHz fundamental crystal or clock input. 4 outputs fixed at 50MHz . Zero PPM synthesis error in all clocks. Ideal for Network switches. 3.3V operation. Available in 16-Pin 150mil SOIC. w .D at h S a t e e 4U . m o c PLL650-09 Low Cost Network LAN Clock PIN CONFIGURATION XIN XOUT G ND VDD 50MHz G ND 50MHz 1 2 16 15 VDD VDD N/C G ND G ND GND VDD P LL 650-09 3 4 5 6 7 8 14 13 12 11 10 9 DESCRIPTIONS The PLL 650-09 is a low cost, low jitter, and high performance clock synthesizer. With PhaseLink’s proprietary analog Phase Locked Loop techniques, the chip accepts 25.
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