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PLL650-05 - Low EMI Network LAN Clock

Description

The PLL 650-05 is a low cost, low jitter, and high performance clock synthesizer.

With PhaseLink’s proprietary analog Phase Locked Loop techniques, the chip accepts 25.0 MHz crystal, and produces multiple output clocks for networking chips, PCI devices, SDRAM, and ASICs.

Features

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  • Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. Advanced, low power, sub-micron CMOS processes. 25MHz fundamental crystal or clock input. 3 fixed outputs of 25MHz, 75Mhz and 125Mhz with output disable SDRAM selectable frequencies of 105, 83.3, 140MHz (Double Drive Strength). Spread spectrum technology selectable for EMI reduction from ±0.5%, ±0.

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Datasheet Details

Part number PLL650-05
Manufacturer PhaseLink
File Size 148.92 KB
Description Low EMI Network LAN Clock
Datasheet download datasheet PLL650-05 Datasheet

Full PDF Text Transcription

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FEATURES • • • • w w• • • • • w • Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. Advanced, low power, sub-micron CMOS processes. 25MHz fundamental crystal or clock input. 3 fixed outputs of 25MHz, 75Mhz and 125Mhz with output disable SDRAM selectable frequencies of 105, 83.3, 140MHz (Double Drive Strength). Spread spectrum technology selectable for EMI reduction from ±0.5%, ±0.75% center for SDRAM and CPU. Zero PPM synthesis error in all clocks. Ideal for Network switches. 3.3V operation. Available in 16-Pin 150mil SOIC. .D at h S a t e e 4U .
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