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PLL650-04 - Low EMI Clock

Description

The PLL 650-04 is a low cost, low jitter, and high performance clock synthesizer.

With PhaseLink proprietary analog Phase Locked Loop techniques, the chip accepts 25.0 MHz crystal, and produces multiple output clocks for networking chips.

Features

  • PIN.

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Datasheet Details

Part number PLL650-04
Manufacturer PhaseLink
File Size 149.72 KB
Description Low EMI Clock
Datasheet download datasheet PLL650-04 Datasheet

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Other Datasheets by PhaseLink

Part Number Description
PLL650-02 Low EMI Network LAN Clock
PLL650-03 Low EMI Network LAN Clock
PLL650-05 Low EMI Network LAN Clock
PLL650-06 Network LAN Clock
PLL650-07 Low COST Network LAN Clock SOURCE

Full PDF Text Transcription

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m Preliminary PLL650-04 o c . EMI Clock for 10/100 PHY and Gigabit Ethernet Low U t4 e FEATURES PIN CONFIGURATION e hswing with 25-mA output drive • Full CMOS output S capability at TTL level. a t • Advanced, low power, sub-micron CMOS processes. a • 25 MHz .D fundamental crystal or clock input. • Low jitter (< 80ps cycle-to-cycle) w • 25 MHz and 50 MHz outputs w CLKOUT selectable between 90, 100, 125, 133, w• Five 145 and 150 MHz. XIN 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 VDD XOUT/SSTE*^ GND 50M_EN^ 25MHz/25M_EN*^ GND PLL 650-04 VDD • • • • • • SSTE (SST Enable) Low EMI selector for CLKOUT. Output enable functionality. Zero PPM synthesis error in all clocks. Ideal for Network switches. 3.3V operation. Available in 20-Pin 150mil SSOP.
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