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PLL103-11 - Low Skew Buffers

Description

O O O I B I P P P P SDRAM Byte0 Clock outputs.

SDRAM Byte1 Clock outputs.

SDRAM Byte2 Clock outputs.

Features

  • Generates 13 copies of High-speed clock inputs. Supports up to three SDRAM DIMMS synchronous clocks.
  • Supports 2-wire I2C serial bus interface with readback.
  • 50% duty cycle with low jitter.
  • Less than 5ns delay. www. DataSheet4U. com.
  • Skew between any outputs is less than 250 ps.
  • Tri-state pin for testing.
  • Frequency up to 150 MHz.
  • 3.0V-3.7V Supply range.
  • Available in 28-pin 300mil SOIC package.
  • PIN CO.

📥 Download Datasheet

Datasheet Details

Part number PLL103-11
Manufacturer PhaseLink Corporation
File Size 178.80 KB
Description Low Skew Buffers
Datasheet download datasheet PLL103-11 Datasheet

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Other Datasheets by PhaseLink Corporation

Part Number Description
PLL103-01 Low Skew Buffer
PLL103-02 DDR SDRAM Buffer
PLL103-03 DDR SDRAM Buffer
PLL103-04 1-to-4 Clock Distribution Buffer
PLL103-05 1-to-5 Clock Distribution Buffer

Full PDF Text Transcription

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PLL103-11 Low Skew Buffers FEATURES Generates 13 copies of High-speed clock inputs. Supports up to three SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50% duty cycle with low jitter. • Less than 5ns delay. www.DataSheet4U.com • Skew between any outputs is less than 250 ps. • Tri-state pin for testing. • Frequency up to 150 MHz. • 3.0V-3.7V Supply range. • Available in 28-pin 300mil SOIC package.
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