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IS61QDB24M18A - 72Mb QUAD (Burst 2) Synchronous SRAM

Description

memory (SRAM) devices.

eliminating the need for high-speed bus turnaround.

all internal operations are self-timed.

Features

  • 2Mx36 and 4Mx18 configuration available.
  • On-chip Delay-Locked loop (DLL) for wide data valid window.
  • Separate independent read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with EARLY write operation.
  • Double Data Rate (DDR) interface for read and write input ports.
  • Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and control registering at rising edge.

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Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61QDB24M18 QUAD (Burst of 2) Synchronous SRAMs
IS61QDB21M18A 18Mb QUAD (Burst 2) Synchronous SRAM
IS61QDB21M18C 18Mb QUAD Synchronous SRAM
IS61QDB21M36 QUAD (Burst of 2) Synchronous SRAMs
IS61QDB21M36A 36Mb QUAD (Burst 2) Synchronous SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS61QDB24M18A IS61QDB22M36A 4Mx18, 2Mx36 72Mb QUAD (Burst 2) Synchronous SRAM AUGUST 2014 FEATURES  2Mx36 and 4Mx18 configuration available.  On-chip Delay-Locked loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with EARLY write operation.  Double Data Rate (DDR) interface for read and write input ports.  Fixed 2-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two output clocks (C and C#) for data output control.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.
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