IS61QDB21M18A Datasheet PDF - ISSI 18Mb QUAD (Burst 2) Synchronous SRAM Specs

IS61QDB21M18A - 18Mb QUAD (Burst 2) Synchronous SRAM

Datasheet Summary

Description

memory (SRAM) devices.

eliminating the need for high-speed bus turnaround.

all internal operations are self-timed.

Features

512Kx36 and 1Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data valid window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with EARLY write operation.
Double Data Rate (DDR) interface for read and write input ports.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control registering at rising ed.

Datasheet Details

Part number	IS61QDB21M18A
Manufacturer	ISSI
File Size	588.46 KB
Description	18Mb QUAD (Burst 2) Synchronous SRAM
Datasheet	IS61QDB21M18A Datasheet
Additional preview pages of the IS61QDB21M18A datasheet.

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Full PDF Text Transcription

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IS61QDB21M18A IS61QDB251236A 1Mx18, 512Kx36 18Mb QUAD (Burst 2) Synchronous SRAM NOVEMBER 2014 FEATURES  512Kx36 and 1Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with EARLY write operation.  Double Data Rate (DDR) interface for read and write input ports.  Fixed 2-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two output clocks (C and C#) for data output control.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.

Published: Jun 10, 2016 |