IS61QDB21M36A Datasheet PDF - ISSI 36Mb QUAD (Burst 2) Synchronous SRAM Specs

IS61QDB21M36A - 36Mb QUAD (Burst 2) Synchronous SRAM

This page provides the datasheet information for the IS61QDB21M36A, a member of the IS61QDB22M18A 36Mb QUAD (Burst 2) Synchronous SRAM family.

Datasheet Summary

Description

memory (SRAM) devices.

eliminating the need for high-speed bus turnaround.

all internal operations are self-timed.

Features

1Mx36 and 2Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data valid window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with EARLY write operation.
Double Data Rate (DDR) interface for read and write input ports.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control registering at rising edge.

Datasheet Details

Part number	IS61QDB21M36A
Manufacturer	ISSI
File Size	650.74 KB
Description	36Mb QUAD (Burst 2) Synchronous SRAM
Datasheet	IS61QDB21M36A Datasheet
Additional preview pages of the IS61QDB21M36A datasheet.

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Full PDF Text Transcription

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IS61QDB22M18A IS61QDB21M36A 2Mx18, 1Mx36 36Mb QUAD (Burst 2) Synchronous SRAM JANUARY 2015 FEATURES  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with EARLY write operation.  Double Data Rate (DDR) interface for read and write input ports.  Fixed 2-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two output clocks (C and C#) for data output control.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.

Published: Jun 10, 2016 |