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IS61QDB24M18 - QUAD (Burst of 2) Synchronous SRAMs

Download the IS61QDB24M18 datasheet PDF (IS61QDB22M36 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for quad (burst of 2) synchronous srams.

Description

The 72Mb IS61QDB22M36 and IS61QDB24M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.

Features

  • 2M x 36 or 4M x 18.
  • On-chip delay-locked loop (DLL) for wide data valid window.
  • Separate read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with early write operation.
  • Double data rate (DDR) interface for read and write input ports.
  • Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K) for address and control registering at rising edges.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61QDB22M36-ISSI.pdf) that lists specifications for multiple related part numbers.

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Full PDF Text Transcription

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72 Mb (2M x 36. & 4M x 18) QUAD (Burst of 2) Synchronous SRAMs A May 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with early write operation. • Double data rate (DDR) interface for read and write input ports. • Fixed 2-bit burst for read and write operations. • Clock stop support. • Two input clocks (K and K) for address and control registering at rising edges only. • Two input clocks (C and C) for data output control. • Two echo clocks (CQ and CQ) that are delivered simultaneously with data. • +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF. • HSTL input and output levels.
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