IS61NVVP51232B Datasheet PDF (18Mb STATE BUS SYNCHRONOUS SRAM)

IS61NVVP51232B - 18Mb STATE BUS SYNCHRONOUS SRAM

This page provides the datasheet information for the IS61NVVP51232B, a member of the IS61NLP51236B 18Mb STATE BUS SYNCHRONOUS SRAM family.

Datasheet Summary

Description

The 18Meg product family

Features

100 percent bus utilization.
No wait cycles between Read and Write.
Internal self-timed write cycle.
Individual Byte Write Control.
Single R/W (Read/Write) control pin.
Clock controlled, registered address, data and control.
Interleaved or linear burst sequence control using MODE input.
Three chip enables for simple depth expansion and address pipelining.
Power Down mode.
Common data inputs and data output.

Datasheet Details

Part number	IS61NVVP51232B
Manufacturer	ISSI
File Size	1.92 MB
Description	18Mb STATE BUS SYNCHRONOUS SRAM
Datasheet	IS61NVVP51232B Datasheet
Additional preview pages of the IS61NVVP51232B datasheet.

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Full PDF Text Transcription

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IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B 512K x36 and 1024K x18 18Mb, PIPELINE 'NO WAIT' STATE BUS SYNCHRONOUS SRAM AUGUST 2019 FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • /CKE pin to enable clock and suspend operation • JEDEC 100-pin QFP, 165-ball BGA and 119- ball BGA packages • Power supply: NLP: VDD 3.3V (± 5%), VDDQ 3.3V/2.

Published: Mar 8, 2019 |