Click to expand full text
IS61NLP102436A/IS61NVP102436A IS61NLP204818A/IS61NVP204818A
1Mb x 36 and 2Mb x 18 36Mb, PIPELINE 'NO WAIT' STATE BUS SRAM
FEBRUARY 2012
FEATURES
• 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address,
data and control • Interleaved or linear burst sequence control using
MODE input • Three chip enables for simple depth expansion
and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP package • Power supply:
NVP: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%) NLP: VDD 3.3V (± 5%), VDDQ 3.3V/2.
IS61NVP204818A Datasheet
