IS61NVP51218A Datasheet PDF - ISSI 9Mb STATE BUS SRAM Specs

IS61NVP51218A - 9Mb STATE BUS SRAM

This page provides the datasheet information for the IS61NVP51218A, a member of the IS61NVP25636A 9Mb STATE BUS SRAM family.

Datasheet Summary

Description

The 9 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications.

Features

100 percent bus utilization.
No wait cycles between Read and Write.
Internal self-timed write cycle.
Individual Byte Write Control.
Single R/W (Read/Write) control pin.
Clock controlled, registered address, data and control.
Interleaved or linear burst sequence control us- ing MODE input.
Three chip enables for simple depth expansion and address pipelining.
Power Down mode.
Common data inputs and data outp.

Datasheet Details

Part number	IS61NVP51218A
Manufacturer	ISSI
File Size	681.44 KB
Description	9Mb STATE BUS SRAM
Datasheet	IS61NVP51218A Datasheet
Additional preview pages of the IS61NVP51218A datasheet.

📁 Similar Datasheet

IS61NVP102436A - 36Mb STATE BUS SRAM (Integrated Silicon Solution)

IS61NVP204818A - 36Mb STATE BUS SRAM (Integrated Silicon Solution)

IS61NVP204836B - PIPELINE (NO WAIT) STATE BUS SRAM (Integrated Silicon Solution)

IS61NVP409618B - PIPELINE (NO WAIT) STATE BUS SRAM (Integrated Silicon Solution)

IS61NVF102418 - STATE BUS SRAM (Integrated Silicon Solution)

IS61NVF204836B - FLOW THROUGH (NO WAIT) STATE BUS SRAM (Integrated Silicon Solution)

IS61NVF409618B - FLOW THROUGH (NO WAIT) STATE BUS SRAM (Integrated Silicon Solution)

IS61NVF51236 - STATE BUS SRAM (Integrated Silicon Solution)

IS61NVVF204836B - FLOW THROUGH (NO WAIT) STATE BUS SRAM (Integrated Silicon Solution)

IS61NVVF409618B - FLOW THROUGH (NO WAIT) STATE BUS SRAM (Integrated Silicon Solution)

Full PDF Text Transcription

Click to expand full text

IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A 256K x 36 and 512K x 18 9Mb, PIPELINE 'NO WAIT' STATE BUS SRAM AUGUST 2014 FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control us- ing MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP, 165-ball PBGA and 119-ball PBGA packages • Power supply: NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.

Published: Jul 12, 2008 |