IS61NVF102436A Datasheet PDF - ISSI 36Mb STATE BUS SRAM Specs

IS61NVF102436A - 36Mb STATE BUS SRAM

This page provides the datasheet information for the IS61NVF102436A, a member of the IS61NLF102436A 36Mb STATE BUS SRAM family.

Datasheet Summary

Description

The 36 Meg 'NLF/NVF' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications.

Features

100 percent bus utilization.
No wait cycles between Read and Write.
Internal self-timed write cycle.
Individual Byte Write Control.
Single Read/Write control pin.
Clock controlled, registered address, data and control.
Interleaved or linear burst sequence control us- ing MODE input.
Three chip enables for simple depth expansion and address pipelining.
Power Down mode.
Common data inputs and data outputs.

Datasheet Details

Part number	IS61NVF102436A
Manufacturer	ISSI
File Size	287.24 KB
Description	36Mb STATE BUS SRAM
Datasheet	IS61NVF102436A Datasheet
Additional preview pages of the IS61NVF102436A datasheet.

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Full PDF Text Transcription

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IS61NLF102436A/IS61NVF102436A IS61NLF204818A/IS61NVF204818A 1M x 36 and 2M x 18 36Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM FEBRUARY 2012 FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single Read/Write control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control us- ing MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP package • Power supply: NVF: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NLF: Vdd 3.3V (± 5%), Vddq 3.3V/2.

Published: Feb 18, 2024 |