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HY5DU283222AF - 128M(4Mx32) GDDR SDRAM

Description

and is subject to change without notice.

Hynix Electronics does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • 2.5V +/- 5% VDD and VDDQ power supply supports 300 / 275 / 250 / 200 MHz 2.8V +/- 5% VDD and VDDQ power supply supports 500/450/400/350MHz All inputs and outputs are compatible with SSTL_2 interface 12mm x 12mm, 144ball FBGA with 0.8mm pin pitch Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS0 ~ DQS3) Data o.

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www.DataSheet4U.com HY5DU283222AF 128M(4Mx32) GDDR SDRAM HY5DU283222AF This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.7 / Jun. 2004 1 HY5DU283222AF Revision History Revision No. 0.1 0.11 0.2 0.3 Defined target spec. 500MHz speed bin added Defined IDD specification 1) Added 222MHz with CL3 and tCK_max=10ns at HY5DU283222AF-36 2) Changed VDD_min value of HY5DU283222AF-36 from 2.375V to 2.
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