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HY5DU121622CTP - 512 Mb GDDR SDRAM

Description

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • VDD, VDDQ = 2.5V +/- 0.1V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL ali.

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HY5DU121622CTP 512Mb(32Mx16) GDDR SDRAM HY5DU121622CTP This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.3 / Apr. 2005 1 1HY5DU121622CTP Revision History Revision No. 0.1 0.2 0.3 History Initial Graphics Version Release Lead free Support & DC parameter change IDD Value change Draft Date Jan. 2005 Apr. 2005 Apr. 2005 Remark Rev. 0.3 / Apr. 2005 2 1HY5DU121622CTP Preliminary DESCRIPTION The HY5DU121622CTP is a 536,870,912-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.
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