Datasheet4U Logo Datasheet4U.com

HY5DU121622C - 512 Mb DDR SDRAM

Description

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • VDD, VDDQ = 2.5V ± 0.2V for DDR200, 266, 333 VDD, VDDQ = 2.6V ± 0.1V for DDR400 All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs o.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
HY5DU281622 4 Banks x 2M x 16Bit Double Data Rate SDRAM Hyundai
HY5DU281622FTP 128Mb DDR SDRAM Hynix
HY5DU281622LT-H 4 Banks x 2M x 16Bit Double Data Rate SDRAM Hyundai
HY5DU281622LT-K 4 Banks x 2M x 16Bit Double Data Rate SDRAM Hyundai
HY5DU281622LT-L 4 Banks x 2M x 16Bit Double Data Rate SDRAM Hyundai

Other Datasheets by SK Hynix

Part Number Description
HY5DU121622CTP 512 Mb GDDR SDRAM
HY5DU121622ALT 512Mb DDR SDRAM
HY5DU121622AT 512Mb DDR SDRAM
HY5DU121622B 512 Mb DDR SDRAM
HY5DU121622DF 512Mb DDR SDRAM

Full PDF Text Transcription

Click to expand full text
512Mb DDR SDRAM HY5DU12422C(L)TP HY5DU12822C(L)TP HY5DU121622C(L)TP This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / Mar. 2005 1 HY5DU12822C(L)TP HY5DU121622C(L)TP 1HY5DU12422C(L)TP Revision History Revision No. 1.0 First Version Release History Draft Date Mar. 2005 Remark Rev. 1.0 / Mar. 2005 2 HY5DU12822C(L)TP HY5DU121622C(L)TP 1HY5DU12422C(L)TP DESCRIPTION The HY5DU12422C(L)TP, HY5DU12822C(L)TP and HY5DU121622C(L)TP are a 536,870,912-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.
Published: |