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HY5DU121622DF - 512Mb DDR SDRAM

Description

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • VDD, VDDQ = 2.3V min ~ 2.7V max (Typical 2.5V Operation +/- 0.2V for DDR266, 333) VDD, VDDQ = 2.4V min ~ 2.7V max (Typical 2.6V Operation +0.1/- 0.2V for DDR400, 400Mbps/pin product and 500Mbps/pin product ) All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS.

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512Mb DDR SDRAM HY5DU12822DF(P) HY5DU121622DF(P) This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / May 2007 1 www.DataSheet.in 1 HY5DU12822DF(P) / HY5DU121622DF(P) Revision History Revision No. 0.01 1.0 History First version for internal review Final Version Release Draft Date Jan. 2007 May 2007 Remark Rev 1.0 / May 2007 2 www.DataSheet.in 1 HY5DU12822DF(P) / HY5DU121622DF(P) DESCRIPTION The HY5DU12822DF(P) and HY5DU121622DF(P) are a 536,870,912-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.
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