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HD74ALVCH16721 - 3.3-V 20-bit Flip Flops with 3-state Outputs

Description

The HD74ALVCH16721’s twenty flip flops are edge triggered D-type flip flops with qualified clock storage.

On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs, provided that the clock enable (CLKEN ) input is low.

If CLKEN is high, no data is stored.

Features

  • VCC = 2.3 V to 3.6 V.
  • Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C).
  • Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C).
  • High output current ±24 mA (@V CC = 3.0 V).
  • Bus hold on data inputs eliminates the need for external pullup / pulldown resistors HD74ALVCH16721 Function Table Inputs OE L L L L H CLKEN H L L L X CLK X ↑ ↑ L or H X D X H L X X Q0.
  • 1 H L Q0.
  • 1 Z Output Q H : High level L : Low level X : Immaterial Z : Hi.

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HD74ALVCH16721 3.3-V 20-bit Flip Flops with 3-state Outputs ADE-205-139B (Z) 3rd. Edition December 1999 Description The HD74ALVCH16721’s twenty flip flops are edge triggered D-type flip flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs, provided that the clock enable (CLKEN ) input is low. If CLKEN is high, no data is stored. A buffered output enable ( OE) input can be used to place the twenty outputs in either a normal logic state (high or low level) or a high impedance state. In the high impedance state, the outputs neither load nor drive the bus lines significantly. The high impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
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