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HD74ALVCH16245 - 16-bit Bus Transceivers with 3-state Outputs

Description

The HD74ALVCH16245 is designed for asynchronous communication between data buses.

The control function implementation minimizes external timing requirements.

This device can be used as two 8-bit transceivers or one 16-bit transceiver.

Features

  • VCC = 2.3 V to 3.6 V.
  • Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C).
  • Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C).
  • Bus hold on data inputs eliminates the need for external pullup / pulldown resistors Function Table Inputs OE L L H H : High level L : Low level X : Immaterial DIR L H X B data to A bus A data to B bus Isolation Operation HD74ALVCH16245 Pin Arrangement 1DIR 1 1B1 2 1B2 3 GND 4 1B3 5 1B4 6 VCC 7 1B5 8 1B6 9 GND 10 1B7.

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📁 Similar Datasheet

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Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
HD74ALVCH16244 16-bit Buffers / Drivers with 3-state Outputs
HD74ALVCH162244 16-bit Buffers / Drivers with 3-state Outputs
HD74ALVCH162260 12-bit to 24-bit Multiplexed D-type Latches with 3-state Outputs
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Full PDF Text Transcription

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HD74ALVCH16245 16-bit Bus Transceivers with 3-state Outputs ADE-205-134C (Z) 4th. Edition December 1999 Description The HD74ALVCH16245 is designed for asynchronous communication between data buses. The control function implementation minimizes external timing requirements. This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allow data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic level at the direction control (DIR) input. The output enable (OE ) input can be used to disable the device so that the buses are effectively isolated. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Features • VCC = 2.3 V to 3.6 V • Typical VOL ground bounce < 0.8 V (@VCC = 3.
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