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DM74LS109A - Dual Positive-Edge-Triggered J-K Flip-Flop

General Description

This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs.

The J and K data is accepted by the flip-flop on the rising edge of the clock pulse.

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Full PDF Text Transcription for DM74LS109A (Reference)

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DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs June 1986 Revised March 2000 DM74LS109A Dual Positive-Edge-Triggered J...

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June 1986 Revised March 2000 DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the J and K inputs may be changed while the clock is HIGH or LOW as long as setup and hold times are not violated.

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Brand Logo Part Number Description Manufacturer
National Semiconductor Logo DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops National Semiconductor

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