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DM74LS112A - Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop

General Description

This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs.

The J and K data is processed by the flip-flop on the falling edge of the clock pulse.

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Full PDF Text Transcription for DM74LS112A (Reference)

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DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs August 1986 Revised March 2000 DM74LS112A Dual Negative-E...

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tary Outputs August 1986 Revised March 2000 DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the falling edge of the clock pulse. Data on the J and K inputs may be changed while the clock is HIGH or LOW without affecting the outputs as long as the setup

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Brand Logo Part Number Description Manufacturer
National Semiconductor Logo DM74LS112A NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS National Semiconductor

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