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CY7C1325 - 256K x 18 Synchronous 3.3V Cache RAM

Description

The CY7C1325 is a 3.3V, 256K by 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic.

Maximum access delay from clock rise is 7.5 ns (117-MHz version).

Features

  • Supports 117-MHz microprocessor cache systems with zero wait states.
  • 256K by 18 common I/O.
  • Fast clock-to-output times.
  • 7.5 ns (117-MHz version).
  • Two-bit wrap-around counter supporting either interleaved or linear burst sequence.
  • Separate processor and controller address strobes provides direct interface with the processor and external cache controller.
  • Synchronous self-timed write.
  • Asynchronous output enable.
  • I/Os.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com CY7C1325 256K x 18 Synchronous 3.3V Cache RAM Features • Supports 117-MHz microprocessor cache systems with zero wait states • 256K by 18 common I/O • Fast clock-to-output times — 7.5 ns (117-MHz version) • Two-bit wrap-around counter supporting either interleaved or linear burst sequence • Separate processor and controller address strobes provides direct interface with the processor and external cache controller • Synchronous self-timed write • Asynchronous output enable • I/Os capable of 2.5–3.3V operation • JEDEC-standard pinout • 100-pin TQFP packaging • ZZ “sleep” mode Functional Description The CY7C1325 is a 3.3V, 256K by 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic.
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