Description
SIGNAL
NAME
NO.TYPE†
DESCRIPTION
CLOCK/PLL
CLKIN
A14
I
Clock Input
CLKOUT1
Y6
O Clock output at full device speed
CLKOUT2
V9
O Clock output at half of device speed
CLKMODE1
B17
CLKMODE0
C17
Clock mode select
I
Selects whether the output clock frequency = input clock freq x4 or x1
PLLFREQ3
C13
PLL frequency range (3, 2, and 1)
PLLFREQ2
G11
I
Selects one of three frequency ranges bounding the CLKOUT1 signal.
CLKOUT1 freq
Features
- -- Byte-Addressable (8-, 16-, 32-Bit Data) -- 32-Bit Address Range -- 8-Bit Overflow Protection -- Saturation -- Bit-Field Extract, Set, Clear -- Bit-Counting -- Normalization
D 1M-Bit On-Chip SRAM
-- 512K-Bit Internal Program/Cache (16K 32-Bit Instructions)
-- 512K-Bit Dual-Access Internal Data (64K Bytes) Organized as a Single Block (’6201)
-- 512K-Bit Dual-Access Internal Data (64K Bytes) Organized as Two Blocks for Improved Concurrency (’6201B)
D 32-Bit External Memory Interface (EMIF)
-- Gl.