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DS92LV1260 - Six Channel 10 Bit BLVDS Deserializer

Description

The DS92LV1260 integrates six deserializer devices into a single chip.

The chip uses a 0.25u CMOS process technology.

The DS92LV1260 can simultaneously deserialize up to six data streams that have been serialized by the Texas Instruments DS92LV1021 or DS92LV1023 Bus LVDS serializers.

Features

  • 1.
  • 2 Deserializes One to Six BusLVDS Input Serial Data Streams with Embedded Clocks.
  • Seven Selectable Serial Inputs to Support n+1 Redundancy of Deserialized Streams.
  • Seventh Channel has Single Pin Monitor Output That Reflects Input From Seventh Channel Input.
  • Parallel Clock Rate up to 40MHz.
  • On Chip Filtering for PLL.
  • Absolute Maximum Worst Case Power Dissipation = 1.9W at 3.6V.
  • High Impedance Inputs Upon Power Off (Vcc = 0V).

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📁 Similar Datasheet

Part Number Description Manufacturer
DS92LV1260 Six Channel 10 Bit BLVDS Deserializer National Semiconductor
DS92LV1212 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer National Semiconductor
DS92LV1224 40-66 MHz 10 Bit Bus LVDS Serializer/Deserializer National Semiconductor
DS92LV1021 16-40 MHz 10 Bit Bus LVDS Serializer/Deserializer National Semiconductor
DS92LV1021A 16-40 MHz 10 Bit Bus LVDS Serializer National Semiconductor

Other Datasheets by Texas Instruments

Part Number Description
DS92LV1210 LVDS Serializer/Deserializer
DS92LV1021 LVDS Serializer/Deserializer
DS92LV16 16-Bit Bus LVDS Serializer/Deserializer
DS92LV18 18-Bit Bus LVDS Serializer/Deserializer
DS92LV010A Bus LVDS 3.3/5.0V Single Transceiver

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DS92LV1260 www.ti.com SNLS134F – DECEMBER 2000 – REVISED APRIL 2013 DS92LV1260 Six Channel 10 Bit BLVDS Deserializer Check for Samples: DS92LV1260 FEATURES 1 •2 Deserializes One to Six BusLVDS Input Serial Data Streams with Embedded Clocks • Seven Selectable Serial Inputs to Support n+1 Redundancy of Deserialized Streams • Seventh Channel has Single Pin Monitor Output That Reflects Input From Seventh Channel Input • Parallel Clock Rate up to 40MHz • On Chip Filtering for PLL • Absolute Maximum Worst Case Power Dissipation = 1.9W at 3.6V • High Impedance Inputs Upon Power Off (Vcc = 0V) • Single Power Supply at +3.
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