CDC2510C Datasheet (Texas Instruments) - 3.3-V Phase-Lock-Loop Clock Driver

CDC2510C, 3.3-V Phase-Lock-Loop Clock Driver

The CDC2510C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver.

It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs.

The CDC2510C operates

D Use CDCVF2510A as a Replacement for this Device D Designed to Meet PC SDRAM Registered DIMM Design Support Document Rev.

1.2 D Spread Spectrum Clock Compatible D Operating Frequency 25 MHz to 125 MHz D Static tPhase Error Distribution at 66 MHz to 100 MHz is ±150 ps D Drop-In Replacement for TI CDC2510A With Enhanced Performance D Jitter (cyc cyc) at 66 MHz to 100 MHz is |100 ps| D Available in Plastic 24-Pin TSSOP D Phase-Lock Loop Clock Distribution for Synchronous DRAM Application