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CDC2509C - 3.3-V Phase-Lock-Loop Clock Driver

Description

The CDC2509C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver.

It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs.

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Full PDF Text Transcription

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CDC2509C 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS620A − DECEMBER 1998 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for this Device D Designed to Meet PC SDRAM Registered DIMM Design Support Document Rev. 1.
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