CDC2509C Datasheet (Texas Instruments) - 3.3-V Phase-Lock-Loop Clock Driver

CDC2509C, 3.3-V Phase-Lock-Loop Clock Driver

The CDC2509C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver.

It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs.

The CDC2509C operates

CDC2509C 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS620A DECEMBER 1998 REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for this Device D Designed to Meet PC SDRAM Registered DIMM Design Support Document Rev.

1.2 D Spread Spectrum Clock Compatible D Operating Frequency 25 MHz to 125 MHz D Static tPhase Error Distribution at 66MHz to 100 MHz is ±150 ps D Drop-In Replacement for TI CDC2509A With Enhanced Performance D Jitter (cyc cyc) at 66 MHz to 100 MHz is |10