CDC2509B Datasheet (Texas Instruments) - 3.3-V Phase-Lock-Loop Clock Driver

CDC2509B, 3.3-V Phase-Lock-Loop Clock Driver

The CDC2509B is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock drivers.

They use a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

They are specifically designed for use with synchronous DRAMs.

The CDC2509B ope

CDC2509B 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS613C SEPTEMBER 1998 REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for this Device D Designed to Meet PC SDRAM Registered DIMM Specification D Spread Spectrum Clock Compatible D Operating Frequency 25 MHz to 125 MHz D Phase Error Time Minus Jitter at 66 MHz to 100 MHz Is ±150 ps D Jitter (peak peak) at 66 MHz to 100 MHz Is ±80 ps D Jitter (cycle cycle) at 66 MHz to 100 MHz Is |100 ps| D Available