WED2ZL361MV - Synchronous Pipeline Burst NBL SRAM

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Datasheet Details

The WEDC SyncBurst SRAM family employs highspeed, low-power CMOS designs that are fabricated using an advanced CMOS process.

Fast clock speed: 166, 150, 133, and 100MHz Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns Fast OE# access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns Single +3.3V ± 5% power supply (VCC) Snooze Mode for reduced-standby power Individual Byte Write control Clock-controlled and registered addresses, data I/Os and control signals Burst control (interleaved or linear burst) Packaging:.
119-bump BGA package Low capacitive bus loading This product is subject to change without notice. WED2ZL361M.

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