WED2DL32512V - 512Kx32 Synchronous Pipeline Burst SRAM

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Datasheet Details

The WEDC SyncBurst - SRAM family employs high-speed, lowpower CMOS designs that are fabricated using an advanced CMOS process.

s Fast clock speed: 200, 166, 150 & 133MHz s Fast access times: 2.5ns, 3.5ns, 3.8ns & 4.0ns s Fast OE access times: 2.5ns, 3.5ns, 3.8ns 4.0ns s Single +3.3V power supply (VDD) s Separate +3.3V or +2.5V isolated output buffer supply (VDDQ) s Snooze Mode for reduced-power standby s Single-cycle deselect s Common data inputs and data outputs s Individual Byte Write control and Global Write s Clock-controlled and registered addresses, data I/Os and control signals s Burst control (interleaved or lin.

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