CY2SSTV16859 - 13-Bit to 26-Bit Registered Buffer

Datasheet Details

This 13-bit to 26-bit registered buffer is designed for 2.3V to 2.7 VDD operations.

Differential clock inputs up to 280 MHz.
Supports LVTTL switching levels on the RESET# pin.
Output drivers have controlled edge rates, so no external resistors are required. www. DataSheet4U. com The CY2SSTV16859 operates from a differential clock (CLK and CLK#) of frequency up to 280 MHz. Data are registered at crossing of CLK going high and CLK# going low. When RESET# is low, the differential input receivers are disabled, and undriven (floating) data and clock inputs.

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Published: Nov 18, 2008 |