K4S281632B-N - 2M x 16Bit x 4 Banks Synchronous DRAM in sTSOP

Samsung semiconductor

Datasheet Details

Part number	K4S281632B-N
Manufacturer	Samsung semiconductor
File Size	64.04 KB
Description	2M x 16Bit x 4 Banks Synchronous DRAM in sTSOP
Datasheet	K4S281632B-N_Samsungsemiconductor.pdf

The K4S281632B-N is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with

JEDEC standard 3.3V power supply.
LVTTL compatible with multiplexed address.
Four banks operation.
MRS cycle with address key programs - CAS latency (2 & 3) - Burst length (1, 2, 4, 8 & Full page) - Burst type (Sequential & Interleave).
All inputs are sampled at the positive going edge of the system clock.
Burst read single-bit write operation.
DQM for masking.
Auto & self refresh.
64ms refresh period (4K cycle).

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Published: Apr 7, 2005 |