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K4S281632B-TC75 - 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL

Download the K4S281632B-TC75 datasheet PDF (K4S included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 128mbit sdram 2m x 16bit x 4 banks synchronous dram lvttl.

Description

The K4S281632B is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Features

  • JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock. Burst read single-bit write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle) CMOS SDRAM.

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Note: The manufacturer provides a single datasheet file (K4S-2816.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Samsung semiconductor
  • K4S281632B-TC10 - 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
  • K4S281632B-TC1H - 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
  • K4S281632B-TC1L - 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
  • K4S281632B-TC80 - 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
  • K4S281632B-TL10 - 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
  • K4S281632B-TL1H - 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
  • K4S281632B-TL1L - 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
  • K4S281632B-TL75 - 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL

Full PDF Text Transcription

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K4S281632B CMOS SDRAM 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.0 Aug. 1999 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.0 Aug. 1999 K4S281632B 2M x 16Bit x 4 Banks Synchronous DRAM FEATURES • • • • JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock.
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