Datasheet4U Logo Datasheet4U.com

PLL601-01 - Low Phase Noise PLL Clock Multiplier

Description

The PLL601-01 is a low cost, high performance and low phase noise clock synthesizer.

With PhaseLink’s proprietary analog and digital Phase Locked Loop techniques, the chip accepts 10-27MHz crystal or clock input, and produces outputs clocks up to 160MHz at 3.3V.

Features

  • e h.
  • Full swing CMOS S outputs with 25 mA drive capability a at TTL levels. t 10-27MHz fundamental crystal or.
  • Reference a clock. . D crystal load capacitor: no external.
  • Integrated w load capacitor required. w.
  • Output clocks up to 160MHz at 3.3V. w.
  • Low phase noise.
  • Output Enable function tri-state outputs. Low jitter: Less than 60 ps cycle to cycle. Advanced, low power, sub-micron CMOS process. 3.3V op.

📥 Download Datasheet

Datasheet Details

Part number PLL601-01
Manufacturer PhaseLink
File Size 196.55 KB
Description Low Phase Noise PLL Clock Multiplier
Datasheet download datasheet PLL601-01 Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
PLL0210A PHASE LOCKED LOOP Z-Communications
PLL0930A PHASE LOCKED LOOP Z-Communications
PLL1000A PHASE LOCKED LOOP Z-Communications
PLL102-03 Low Skew Output Buffer PhaseLink Corporation
PLL102-04 Low Skew Output Buffer PhaseLink Corporation

Other Datasheets by PhaseLink

Part Number Description
PLL601-02 Low Phase Noise PLL Clock Multiplier
PLL601-12 Dual Output PLL Clock
PLL601-15 Low Phase Noise PLL Clock Multiplier
PLL600-10 (PLL600-10/20/30) Ultra Low Current XO
PLL600-17 (PLL600-17/27/37) Ultra Low Current XO

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
m o .c U 4 t e FEATURES e h • Full swing CMOS S outputs with 25 mA drive capability a at TTL levels. t 10-27MHz fundamental crystal or • Reference a clock. .D crystal load capacitor: no external • Integrated w load capacitor required. w • Output clocks up to 160MHz at 3.3V. w• Low phase noise. • • • • • Output Enable function tri-state outputs. Low jitter: Less than 60 ps cycle to cycle. Advanced, low power, sub-micron CMOS process. 3.3V operation. Available in 16-Pin SOIC or TSSOP. Preliminary PLL601-01 Low Phase Noise PLL Clock Multiplier PIN CONFIGURATION CLK REFEN VDD VDD VDD 1 2 16 15 GND GND GND REFOUT OE S0 S3 S2 PLL 601-01 3 4 5 6 7 8 14 13 12 11 10 9 DESCRIPTIONS The PLL601-01 is a low cost, high performance and low phase noise clock synthesizer.
Published: |