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MC100E212 - 3-BIT SCANNABLE REGISTERED ADDRESS DRIVER

Description

PIN D0 D2 S-IN LOAD SHIFT CLK MR S-OUT Q[0:2]a, Q[0:2]b Q[0:2]a, Q[0:2]b VCC, VCCO VEE NC FUNCTION ECL Data Inputs ECL Scan Input ECL LOAD/HOLD Control ECL Scan Control ECL Clock ECL Reset ECL Scan Output ECL True Outputs ECL Inverting Outputs Positive Supply Negative Supply No Connect FU

Features

  • 1405 AN1406 AN1503 AN1504 AN1568 AN1596 AN1650 AN1672 AND8001 AND8002 AND8020.
  • ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) ECLinPS I/O SPICE Modeling Kit Metastability and the ECLinPS Family Interfacing Between LVDS and ECL ECLinPS Lite Translator ELT Family SPICE I/O Model Kit Using Wire.
  • OR Ties in ECLinPS Designs The ECL Translator Guide Odd Number Co.

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Datasheet Details

Part number MC100E212
Manufacturer onsemi
File Size 209.61 KB
Description 3-BIT SCANNABLE REGISTERED ADDRESS DRIVER
Datasheet download datasheet MC100E212 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com MC10E212, MC100E212 5V ECL 3-Bit Scannable Registered Address Driver The MC10E/100E212 is a scannable registered ECL driver typically used as a fan-out memory address driver for ECL cache driving. In a VLSI array based CPU design, use of the E212 allows the user to conserve array output cell functionality and also output pins. The input shift register is designed with control logic which greatly facilitates its use in boundary scan applications. The 100 Series contains temperature compensation. http://onsemi.com MARKING DIAGRAMS 1 28 • • • • • • Scannable Version E112 Driver 1025 ps Max. CLK to Output Dual Differential Outputs Master Reset PECL Mode Operating Range: VCC= 4.2 V to 5.7 V with VEE= 0 V NECL Mode Operating Range: VCC= 0 V with VEE= −4.2 V to −5.
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