two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features fully differential clock paths to minimize both device and system skew. The dual buffer allows for the fanout of two signals through a single chip, thus reducing the skew between the two fundamental signals from a part.
to.
part skew down to an output.
to.
output skew. This capability reduces the skew by a factor of 4 as compared to using two LVE111’s to accomplish the same task. The low.
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MC100E210 5V ECL Dual 1:4, 1:5 Differential Fanout Buffer The MC100E210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in...
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ual differential ECL fanout buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features fully differential clock paths to minimize both device and system skew. The dual buffer allows for the fanout of two signals through a single chip, thus reducing the skew between the two fundamental signals from a part−to−part skew down to an output−to−output skew. This capability reduces the skew by a factor of 4 as compared to using two LVE111’s to accomplish the same task.
MC100E210 Datasheet
