ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) ECLinPS I/O SPICE Modeling Kit Metastability and the ECLinPS Family Interfacing Between LVDS and ECL ECLinPS Lite Translator ELT Family SPICE I/O Model Kit Using Wire.
OR Ties in ECLinPS Designs The ECL Translator Guide Odd Number Co.
Full PDF Text Transcription for MC100E212 (Reference)
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www.DataSheet4U.com MC10E212, MC100E212 5V ECL 3-Bit Scannable Registered Address Driver The MC10E/100E212 is a scannable registered ECL driver typically used as a fan-ou...
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00E212 is a scannable registered ECL driver typically used as a fan-out memory address driver for ECL cache driving. In a VLSI array based CPU design, use of the E212 allows the user to conserve array output cell functionality and also output pins. The input shift register is designed with control logic which greatly facilitates its use in boundary scan applications. The 100 Series contains temperature compensation. http://onsemi.com MARKING DIAGRAMS 1 28 • • • • • • Scannable Version E112 Driver 1025 ps Max. CLK to Output Dual Differential Outputs Master Reset PECL Mode Operating Range: VCC= 4.2 V to 5.7 V with VEE= 0 V N