Description
S7B803635M SS77BB880013863355MM S7B801835M 256Kx36 & 512Kx18 Flow-Through SRAM 256Kx36 & 512Kx18 Flow-Through SRAM 9Mb Sync.Flow-Through SRAM Speci.
The S7B803635M and S7B801835M are 9,437,184-bit Synchronous Static Random Access Memory designed for high performance.
Features
* VDD = 2.5V(2.3V ~ 2.7V) or 3.3V(3.1V ~ 3.5V) Power Supply
* VDDQ = 2.3V~2.7V I/O Power Supply (VDD=2.5V) or
2.3V~3.5V I/O Power Supply (VDD=3.3V)
* Synchronous Operation
* Self-Timed Write Cycle
* On-Chip Address Counter and Control Registers
* Byte
Applications
* GW, BW, LBO, ZZ. Write cycles are internally selftimed and synchronous. Full bus-width write is done by GW, and each byte write is performed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control signals. Burst cycle can be initiated with either the address
