S7B401835M Description
S7B403635M SS77BB440013863355MM S7B401835M 128Kx36 & 256Kx18 Flow-Through SRAM 128Kx36 & 256Kx18 Flow-Through SRAM 4Mb Sync.Flow-Through SRAM Speci.
The S7B403635M and S7B401835M are 4,718,592-bit Synchronous Static Random Access Memory designed for high performance.
S7B401835M Features
* VDD = 2.5V(2.3V ~ 2.7V) or 3.3V(3.1V ~ 3.5V) Power Supply
* VDDQ = 2.3V~2.7V I/O Power Supply (VDD=2.5V) or
2.3V~3.5V I/O Power Supply (VDD=3.3V)
* Synchronous Operation
* Self-Timed Write Cycle
* On-Chip Address Counter and Control Registers
* Byte
S7B401835M Applications
* GW, BW, LBO, ZZ. Write cycles are internally selftimed and synchronous. Full bus-width write is done by GW, and each byte write is performed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control signals. Burst cycle can be initiated with either the address
📁 Related Datasheet
📌 All Tags
