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ZL30182 - Dual-Channel Any-to-Any Clock Rate Translator

Description

5.

5.3.1 APLL-Only Mode 11 5.3.2 DPLL+APLL Mode 11 5.3.

Features

  • Two Independent Channels.
  • Three Input Clocks Per Channel.
  • Three inputs, two differential/CMOS, one CMOS.
  • Any input frequency from 1kHz to 1250MHz (1kHz to 300MHz for CMOS).
  • Inputs continually monitored for activity and frequency accuracy.
  • Automatic or manual reference switching.
  • Low-Bandwidth DPLL Per Channel.
  • Programmable bandwidth, 5Hz to 500Hz.
  • Attenuates jitter up to several UI.
  • Freerun or holdover on.

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Full PDF Text Transcription

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Register Map: Section 6.
Published: |