Datasheet Details
| Part number | ZL30100 |
|---|---|
| Manufacturer | Zarlink Semiconductor Inc |
| File Size | 436.73 KB |
| Description | T1/E1 System Synchronizer |
| Datasheet |
 ZL30100 Datasheet
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General Description
The ZL30100 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk T1 and E1 transmission equipment.
The ZL30100 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of two input references.
Key Features
- April 2010.
- Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E.
- Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces.
- Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces Ordering Information ZL30100QDG1 64 Pin TQFP.
- Trays, Bake & Drypack.
- Pb Free Matte Tin -40°C to +85°C.
- Simple hardware control interface.
- Accepts two input references and synchronizes to any combination of 8 kHz, 1.544 MHz,.