QS5919T Datasheet (Integrated Device Technology)

QS5919T, LOW SKEW TTL PLL CLOCK DRIVER

The QS5919T Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs.

Eight outputs are available: 2xQ, Q 0-Q4, Q5, Q/2.

Careful layout and design ensure < 350ps skew between the Q0-Q4, and Q/2 outputs.

The QS5919T includes an internal RC fi

QS5919T Features

* 5V operation Low noise TTL level outputs < 350ps output skew, Q0

* Q4 2xQ output, Q outputs, Q output, Q/2 output Outputs 3-state and reset while OE/RST low PLL disable feat