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HYMP112U64CP8-C4 - 240pin DDR2 SDRAM Unbuffered DIMMs based on 1Gb C version

This page provides the datasheet information for the HYMP112U64CP8-C4, a member of the HYMP164U64CP6-C4 240pin DDR2 SDRAM Unbuffered DIMMs based on 1Gb C version family.

Datasheet Summary

Description

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • JEDEC standard Double Data Rate2 Synchrnous DRAMs (DDR2 SDRAMs) with 1.8V +/ - 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface 8 Bank architecture Posted CAS Programmable CAS Latency 3 ,4 ,5, 6 OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Termination) Fully differential clock operations (CK & CK).
  • Programmable Burst Length 4 / 8 with both sequential and interleave mode Auto re.

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Datasheet preview – HYMP112U64CP8-C4

Datasheet Details

Part number HYMP112U64CP8-C4
Manufacturer Hynix Semiconductor
File Size 252.14 KB
Description 240pin DDR2 SDRAM Unbuffered DIMMs based on 1Gb C version
Datasheet download datasheet HYMP112U64CP8-C4 Datasheet
Additional preview pages of the HYMP112U64CP8-C4 datasheet.

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240pin DDR2 SDRAM Unbuffered DIMMs based on 1Gb C version This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 1Gb version C DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb version C based DDR2 Unbuffered DIMM series provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition. FEATURES • JEDEC standard Double Data Rate2 Synchrnous DRAMs (DDR2 SDRAMs) with 1.8V +/ - 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.
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