HYMP512R72x Datasheet PDF - Hynix 128M x 72 Bits DDR2 SDRAM Registered DIMM Specs

HYMP512R72x - 128M x 72 Bits DDR2 SDRAM Registered DIMM

This page provides the datasheet information for the HYMP512R72x, a member of the HYMP512R72 128M x 72 Bits DDR2 SDRAM Registered DIMM family.

Datasheet Summary

Description

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

1GB (128M x 72) Registered DDR2 DIMM based on 128Mx4 DDR2 SDRAMs JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply JEDEC Standard 240-pin dual in-line memory module (DIMM) Error Check Correction (ECC) Capability All inputs and outputs are compatible with SSTL_1.8 interface OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination).
Fully differential clock op.

Datasheet Details

Part number	HYMP512R72x
Manufacturer	Hynix
File Size	232.74 KB
Description	128M x 72 Bits DDR2 SDRAM Registered DIMM
Datasheet	HYMP512R72x Datasheet
Additional preview pages of the HYMP512R72x datasheet.

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Full PDF Text Transcription

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128Mx72 bits DDR2 SDRAM Registered DIMM HYMP512R72(L)4 Revision History No. 0.1 History 1) Defined Target Spec. 1) Added Pin Capacitance Spec. & IDD Spec. 2) Corrected SPD typo(byte #22,#42) Corrected Pin assignment table Draft Date Feb. 2004 Apr. 2004 July 2004 Remark 0.2 This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2 / July 2004 1 128Mx72 bits DDR2 SDRAM Registered DIMM HYMP512R72(L)4 DESCRIPTION Hynix HYMP512R72(L)4 series is registered 240-pin double data rate 2 Synchronous DRAM Dual In-Line Memory Modules(DIMMs) which are organized as 128Mx72 high-speed memory arrays.

Published: Aug 19, 2005 |