HYMP512S64CLP8-Y5 Datasheet PDF - Hynix 200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb Specs

HYMP512S64CLP8-Y5 - 200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb

This page provides the datasheet information for the HYMP512S64CLP8-Y5, a member of the HYMP532S64CP6-E3 200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb family.

Datasheet Summary

Description

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface Posted CAS Programmable CAS Latency 3, 4, 5, 6 OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) Fully differential clock operations (CK & CK).
Programmable Burst Length 4 / 8 with both sequential and interleave mode Auto refresh and self r.

Datasheet Details

Part number	HYMP512S64CLP8-Y5
Manufacturer	Hynix
File Size	295.06 KB
Description	200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb
Datasheet	HYMP512S64CLP8-Y5 Datasheet
Additional preview pages of the HYMP512S64CLP8-Y5 datasheet.

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Full PDF Text Transcription

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200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb C ver. This Hynix unbuffered Small Outline Dual In-Line Memory Module(DIMM) series consists of 512Mb C ver. DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 200pin glass-epoxy substrate. This Hynix 512Mb C ver. based Unbuffered DDR2 SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of industry standard. It is suitable for easy interchange and addition. FEATURES • JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.

Published: Oct 18, 2014 |