MC100ES6221 - Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer

Freescale Semiconductor

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Datasheet Details

Part number	MC100ES6221
Manufacturer	Freescale Semiconductor
File Size	340.29 KB
Description	Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer
Datasheet	MC100ES6221_FreescaleSemiconductor.pdf

MC100ES6221 Product details

Description

AE SUFFIX 52-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 1336A-01 The MC100ES6221 is designed for low skew clock distribution systems and supports clock frequencies up to 2 GHz.The device accepts two clock sources.The CLK0 input can be driven by ECL or PECL compatible signals, the CLK1 input accepts HSTL compatible signals.The selected input signal is distributed to 20 identical, differential ECL/PECL outputs.If VBB is connected to the CLK0 or CLK1 input and bypassed to GND by a 10 nF capacitor

Features

1:20 differential clock fanout buffer 100 ps maximum device skew SiGe technology Supports DC to 2 GHz operation of clock or data signals ECL/PECL compatible differential clock outputs ECL/PECL/HSTL compatible differential clock inputs Single 3.3 V,.
3.3 V, 2.5 V or.
2.5 V supply Standard 52 lead LQFP package with exposed pad for enhanced thermal characteristics Supports i.

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Other Datasheets by Freescale Semiconductor

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Published: Feb 24, 2010 |