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MC100ES6014 - 2.5 V/3.3 V 1:5 Differential ECL/PECL/HSTL/LVDS Clock Driver

Description

Pin CLK0 , CLK0 CLK1 , CLK1 Q0:4, Q0:4 CLK_SEL EN

Table 2.

Features

  • 25 ps Within Device Skew 400 ps Typical Propagation Delay Maximum Frequency > 2 GHz Typical The 100 Series Contains Temperature Compensation PECL and HSTL Mode: VCC = 2.375 V to 3.8 V with VEE = 0 V ECL Mode: VCC = 0 V with VEE =.
  • 2.375 V to.
  • 3.8 V LVDS and HSTL Input Compatible Open Input Default State 20-Lead Pb-Free Package Available MC100ES6014 DT SUFFIX 20-LEAD TSSOP.

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Other Datasheets by Freescale Semiconductor (now NXP Semiconductors)

Part Number Description
MC100ES6017 3.3V ECL/PECL Quad Differential Receiver
MC100ES6039 3.3V ECL/PECL/HSTL/LVDS Generation Chip
MC100ES6056 2.5 V/3.3 V ECL/PECL/LVDS Dual Differential 2:1 Multiplexer
MC100ES60T22 3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Translator
MC100ES6139 Clock Generation Chip

Full PDF Text Transcription

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Freescale Semiconductor Technical Data MC100ES6014 Rev 3, 06/2005 www.DataSheet4U.com 2.5 V/3.3 V 1:5 Differential ECL/PECL/HSTL/LVDS Clock Driver The MC100ES6014 is a low skew 1-to-5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single-ended (if the VBB output is used). HSTL and LVDS inputs can be used when the ES6014 is operating under PECL conditions. The ES6014 specifically guarantees low output-to-output skew. Optimal design, layout, and processing minimize skew within a device and from device to device.
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