MC100ES6056 Datasheet (Renesas) - ECL/LVPECL/LVDS Dual Differential 2:1 Multiplexer

MC100ES6056, ECL/LVPECL/LVDS Dual Differential 2:1 Multiplexer

Pin Function D0a * * D1a * ECL Input Data a D0a * * D1a * ECL Input Data a Invert D0b * * D1b * ECL Input Data b D0b * * D1b * ECL Input Data b Invert SEL0 * * SEL1 * ECL Indiv.

Select Input COM_SEL * ECL Common Sel

2.5V, 3.3V ECL/LVPECL/LVDS Dual Differential 2:1 Multiplexer NRND Not Recommend for New Designs Product Discontinuance Notice Last Time Buy Expires on (12/23/2013) MC100ES6056 NRND DATASHEET The MC100ES6056 is a dual, fully differential 2:1 multiplexer.

The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals.

Multiple VBB pins are provided.

The VBB pin, an internally generated voltage supply, is available to this dev

MC100ES6056 Features

* both individual and common select inputs to address both data path and random logic applications. The 100ES Series contains temperature compensation. Features

* 360 ps Typical Propagation Delays

* Maximum Frequency > 3 GHz Typical

* PECL Mode Operating Range: VCC = 2.375 V to