AS4LC8M8S0 - 3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM

AS4LC8M8S0 Datasheet Preview — Preview of AS4LC8M8S0 PDF

Datasheet Details

Part number	AS4LC8M8S0
Manufacturer	ETC
File Size	566.21 KB
Description	3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM
Datasheet	AS4LC8M8S0_ETC.pdf

AS4LC8M8S0 Product details

Description

Output disable/write mask Address inputs Bank select inputs Input/output Row address strobe Column address strobe Write enable Chip select Power (3.3V ± 0.3V) Ground Clock input Clock enable AS4LC4M16S0 Selection guide Symbol Bus frequency Minimum clock access time Minimum setup time Minimum hold time Minimum RAS to CAS delay Minimum RAS precharge time Remarks: (CL/tRCD/tRP) CL = 2 CL = 3 fmax tAC tAC tS tH tRCD tRP -75 (PC133) 133 5.4 1.5 0.8 3 3 3/3/3 -8 125 6 2 1.0 3 3 3

Features

PC100/133 compliant.
Organization - 2,097,152 words × 8 bits × 4 banks (8M×8) - 1,048,576 words × 16 bits × 4 banks (4M×16).
Fully synchronous - All signals referenced to positive edge of clock.
Four internal banks controlled by BA0/BA1 (bank select).
High speed - 133/125/100 MHz - 5.4 ns (133 MHz)/6 ns (125/100 MHz) clock access time.
Low power consumption - Standby: 7.2 mW max, CMOS I/O.
4096 refresh cycles, 64 ms refresh interva.

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Other Datasheets by ETC

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Published: Mar 24, 2005 |