AS4LC2M8S0 - (AS4LCxMxxSx) 3.3V 2M X 8/1M X 16 CMOS synchronous DRAM

Alliance Semiconductor

AS4LC2M8S0 Datasheet Preview — Preview of AS4LC2M8S0 PDF

Datasheet Details

Part number	AS4LC2M8S0
Manufacturer	Alliance Semiconductor
File Size	1.01 MB
Description	(AS4LCxMxxSx) 3.3V 2M X 8/1M X 16 CMOS synchronous DRAM
Datasheet	AS4LC2M8S0_AllianceSemiconductor.pdf

AS4LC2M8S0 Product details

Description

Output disable/write mask AS4LC2M8S1 and AS4LC2M8S0 AS4LC1M16S0 and AS4LC1M16S1 DataSheet4U.com VSSQ DQ9 DQ8 VCCQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 VSS RA0 10 DataShee Address inputs CA0 7 (×16) CA0 8 (×8) Bank address (BA) Input/output Row address strobe Column address strobe Write enable Chip select Power (3.3V ± 0.3V) Ground Clock input Clock enable LEGEND Configuration Refresh Count Row Address Bank Address Column Address 2M × 8 1M × 8 × 2 banks 2K/4K (

Features

Organization - 1,048,576 words × 8 bits × 2 banks (2M × 8) 11 row, 9 column address - 524,288 words × 16 bits × 2 banks (1M × 16) 11 row, 8 column address AS4LC2M8S1 AS4LC2M8S0 AS4LC1M16S1 AS4LC1M16S0.
All signals referenced to positive edge of clock, fully synchronous.
Dual internal banks controlled by A11 (bank select).
High speed - 143/125/100 MHz - 7/8/10 ns clock access time.
Auto refresh and self refresh.
PC100 functionality.

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Other Datasheets by Alliance Semiconductor

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Published: Sep 20, 2006 |